RP2040 or RP2350?
If on the same PIO you can try to reset the clock dividers synchronously by using:
ON RP2350 can synchronize also between PIO blocks:
If on the same PIO you can try to reset the clock dividers synchronously by using:
PIO: CTRL Register
11:8 CLKDIV_RESTART: Restart a state machine’s clock divider from an initial
phase of 0. Clock dividers are free-running, so once started, their output
(including fractional jitter) is completely determined by the integer/fractional
divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers
with the same divisor are restarted simultaneously, by writing multiple 1 bits to
this field, the execution clocks of those state machines will run in precise
lockstep.
Note that setting/clearing SM_ENABLE does not stop the clock divider from
running, so once multiple state machines' clocks are synchronised, it is safe to
disable/reenable a state machine, whilst keeping the clock dividers in sync.
Note also that CLKDIV_RESTART can be written to whilst the state machine is
running, and this is useful to resynchronise clock dividers after the divisors
(SMx_CLKDIV) have been changed on-the-fly.
ON RP2350 can synchronize also between PIO blocks:
NEXTPREV_CLKDIV_RESTART: Write 1 to restart the clock dividers of state
machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and
PREV_PIO_MASK in the same write.
This is equivalent to writing 1 to the corresponding CLKDIV_RESTART bits in
those PIOs' CTRL registers.
Statistics: Posted by gmx — Fri May 09, 2025 12:12 am