By my tests if two state machines are set to use the same clock (thus they will apply the same fractional clock divider from sys_clk) they will indeed have the same clock period but they will not be phase aligned.
Example: set sm1 and sm2 to use sys_clk/4, this is what I see in the logical analyzer:The period is the same but the clocks are shifted.
Is there a way apply exactly the same clock signal to both?
Example: set sm1 and sm2 to use sys_clk/4, this is what I see in the logical analyzer:
Code:
sm1_clk: 000011110000111100001111sm2_clk: 111000011110000111100001Is there a way apply exactly the same clock signal to both?
Statistics: Posted by morci — Thu May 08, 2025 11:30 pm