Rereading your original post:None of those overrides exist.
panel-width should be hactive
panel-height should be vactive
refresh_rate is determined via clock-frequency (pixel rate) and all the mode timings.
You are best off using the override to specify the panel timings, or "kmstest -r ..." to specify the full timings.
How many data lanes have you connected up? The overlay's default is only for 1 data lane, so is your DS90UH941AS also set for 1 data lane (datasheet "8.6.1.55 BRIDGE_CTL" says it defaults to whatever strapping is set up on MODE_SEL0 and MODE_SEL1 "8.4.1 Mode Select Configuration Settings").
Do note the "Using a DSI display" whitepaper on https://pip.raspberrypi.com/categories/ ... hitepapers. vc4's DSI (ie Pi0-4) is fed from an integer divider from a PLL, so can only generate certain DSI link frequencies. The driver will fix up the mode to accommodate this, but doing so can cause grief if bridge chips are trying to derive their timings from the DSI clock lane.
According to the datasheet for DS90UH941AS, "8.6.1.13 GENERAL_STS" lists a DSI_ERROR error bit, and "8.6.2.20 DSI_STATUS" gives more detailed DSI status. So what is the chip saying about what it is seeing on DSI?
Code:
dtoverlay=vc4-kms-dsi-generic,panel_width=800,panel_height=480,refresh_rate=60panel-width should be hactive
panel-height should be vactive
refresh_rate is determined via clock-frequency (pixel rate) and all the mode timings.
You are best off using the override to specify the panel timings, or "kmstest -r ..." to specify the full timings.
How many data lanes have you connected up? The overlay's default is only for 1 data lane, so is your DS90UH941AS also set for 1 data lane (datasheet "8.6.1.55 BRIDGE_CTL" says it defaults to whatever strapping is set up on MODE_SEL0 and MODE_SEL1 "8.4.1 Mode Select Configuration Settings").
Do note the "Using a DSI display" whitepaper on https://pip.raspberrypi.com/categories/ ... hitepapers. vc4's DSI (ie Pi0-4) is fed from an integer divider from a PLL, so can only generate certain DSI link frequencies. The driver will fix up the mode to accommodate this, but doing so can cause grief if bridge chips are trying to derive their timings from the DSI clock lane.
According to the datasheet for DS90UH941AS, "8.6.1.13 GENERAL_STS" lists a DSI_ERROR error bit, and "8.6.2.20 DSI_STATUS" gives more detailed DSI status. So what is the chip saying about what it is seeing on DSI?
Statistics: Posted by 6by9 — Mon Mar 24, 2025 11:52 am