SDK • Re: Pico PIO IN read timing

gmx,

The code needs to work on both processors. The current DUT is a 2040 PIco W.

The code is all master, so the signals are synchronous, with a reasonably well defined set up time (+/- a few nS).

Thanks for the interesting DSO captures.

arg001,

I'm assuming that a cycle here is a sysclk cycle, rather than a PIO cycle - as that's the only way your answer makes sense!

The answer is that there is one cycle of delay on outputs (ie. appears on pins 1 cycle after instruction execution), and 1 cycle without synchronizers or 3 cycles including synchronizers on inputs.

So if a program changes the state of a pin and then reads the state of that pin it will see the change 4 instructions later (or 2 later if synchronizers disabled).

You have given me the guidance I need. If I'm reading you correctly, Inputs are sampled each SYSCLK cycle and are available to the PIO 4 SYSCLKS later. They will be read by a PIO IN instruction at the start of the instruction cycle which will receive whatever value was present at the GPIO pin 4 SYSCLKS earlier.

Statistics: Posted by palmerr23 — Tue Jan 27, 2026 2:45 am

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