Bare metal, Assembly language • RPi5 Question: Debugging GEM RX DMA via RP1 / PCIe inbound address translation

Hello,

I am developing a hobby bare-metal OS running on Raspberry Pi 5, and I am currently working on a driver for the Gigabit Ethernet MAC (GEM). The PHY reset and auto-negotiation have completed successfully (LEDs on the LAN port are on), and I am trying to receive packets, but it is not working as expected.

The RXCNT (Receive Count) register is increasing, which suggests that the PHY is receiving packets. However, the RSR (Receive Status Register) shows that the "Buffer Not Available" bit is set, and the USED bit in the RxQueue descriptors is never set. Because of this, I suspect that DMA is not working correctly.

At the moment, my PCIe Inbound Address Translation is configured as follows:
- PCI address: 0
- CPU address: 0
- Size: 64GiB

In addition, in the RP1 PCIe configuration space, I have enabled Bus Master Enable and Memory Space Enable.

My questions are:
- Is this Inbound Address Translation configuration correct?
- Are there any specific registers (PCIe or GEM) that I should check to help narrow down the issue?
- Is there any way to debug which CPU address the GEM/RP1 is actually trying to access, and why the access is failing?

I think it's unlikely to be a cache issue, as I am performing explicit cache clean/invalidate operations before and after accessing the RX descriptor ring and buffers.

For reference, below is a dump of the GEM registers:
Additionally, the beginning of the RxQueue looks like this (the addresses in the left column are virtual addresses). The descriptors are initialized according to the Cadence GEM descriptor format (USED = 0, WRAP set on the last descriptor not shown here).

Statistics: Posted by smallkirby — Sat Jan 24, 2026 6:26 am

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