General • Re: Baremetal interrupt and GCC

That works for simple code because it contains BX LR as the return from a normal function and
as you noted it sets the LR register value.

However I am writing an RTOS and sometimes you are in handler mode and sometimes you are
in thread mode and the dam NVIC allows higher priority preempting. It was getting confused
about what LR value to set which is why I thought there must be a way to define an interrupt code

I ended up finding discussion from ARM about the "bug" which comes from the (NVIC) limitations
and a low-priority interrupt preempted by a higher-priority one, the lower-priority interrupt
is not handled correctly upon the higher-priority interrupt's completion.

I loved ARMs work around make all your interrupts the same level (so no nesting) or move to a cortex M3 or M4

For now I just stopped nesting which makes interrupt latency less than ideal.

Statistics: Posted by LdB — Wed Nov 05, 2025 3:42 pm

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