Compute Module • [CM4] PCIe link down with VL805 for using multi USB 3.0 port

Hello, this is my first time visiting the forum, so I'm not sure if this is the right place to post, but I'm hoping to get some help.

I've been using Raspberry Pi for about three months, and I'm still learning a lot. I recently ran into a problem, and I've been searching for solutions for days, trying everything I can find, but I can't seem to narrow down the solution. So, I'm asking for help from experienced users.

The hardware I'm currently developing includes the basic configuration found on the CM4 IO Board. I'm having a problem with the CM4 - VL805 - USB 3.0 three port configuration. As you know, CM4 - VL805 is linked via PCIe. Some samples successfully connect via PCIe and eventually the USB 3.0 comes up, but other samples have the PCIe link down. I want to know the reason why.

I'm posting three dmesg results:
1. When the official Raspberry Pi OS is installed on a problematic sample.
2. When a custom OS (based on the official Raspberry Pi OS) is installed on a working sample.
3. When the custom OS is installed on a problematic sample.

[Raspberry OS]
...
[ 0.572335] brcm-pcie fd500000.pcie: host bridge /scb/pcie@7d500000 ranges:
[ 0.572367] brcm-pcie fd500000.pcie: No bus range found for /scb/pcie@7d500000, using [bus 00-ff]
[ 0.572391] brcm-pcie fd500000.pcie: MEM 0x0600000000..0x063fffffff -> 0x00c0000000
[ 0.572411] brcm-pcie fd500000.pcie: IB MEM 0x0000000000..0x007fffffff -> 0x0400000000
[ 0.573370] brcm-pcie fd500000.pcie: PCI host bridge to bus 0000:00
[ 0.573401] pci_bus 0000:00: root bus resource [bus 00-ff]
[ 0.573413] pci_bus 0000:00: root bus resource [mem 0x600000000-0x63fffffff] (bus address [0xc0000000-0xffffffff])
[ 0.573466] pci 0000:00:00.0: [14e4:2711] type 01 class 0x060400 PCIe Root Port
[ 0.573486] pci 0000:00:00.0: PCI bridge to [bus 00]
[ 0.573497] pci 0000:00:00.0: bridge window [mem 0x00000000-0x000fffff]
[ 0.573509] pci 0000:00:00.0: bridge window [mem 0x00000000-0x000fffff 64bit pref]
[ 0.573552] pci 0000:00:00.0: PME# supported from D0 D3hot
[ 0.575039] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[ 0.575132] pci_bus 0000:01: supply vpcie3v3 not found, using dummy regulator
[ 0.575212] pci_bus 0000:01: supply vpcie3v3aux not found, using dummy regulator
[ 0.575242] pci_bus 0000:01: supply vpcie12v not found, using dummy regulator
[ 0.919425] brcm-pcie fd500000.pcie: link down
[ 0.919572] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
[ 0.919595] pci 0000:00:00.0: PCI bridge to [bus 01]
[ 0.919608] pci_bus 0000:00: resource 4 [mem 0x600000000-0x63fffffff]
[ 0.919868] pcieport 0000:00:00.0: PME: Signaling with IRQ 27
[ 0.920068] pcieport 0000:00:00.0: AER: enabled with IRQ 27
[ 0.920347] pci_bus 0000:01: busn_res: [bus 01] is released
[ 0.920604] pci_bus 0000:00: busn_res: [bus 00-ff] is released
...

[Custom OS : Fail]
[ 0.572335] brcm-pcie fd500000.pcie: host bridge /scb/pcie@7d500000 ranges:
[ 0.572367] brcm-pcie fd500000.pcie: No bus range found for /scb/pcie@7d500000, using [bus 00-ff]
[ 0.572391] brcm-pcie fd500000.pcie: MEM 0x0600000000..0x063fffffff -> 0x00c0000000
[ 0.572411] brcm-pcie fd500000.pcie: IB MEM 0x0000000000..0x007fffffff -> 0x0400000000
[ 0.573370] brcm-pcie fd500000.pcie: link down

[Custom OS : Normal]
[ 0.572335] brcm-pcie fd500000.pcie: host bridge /scb/pcie@7d500000 ranges:
[ 0.572367] brcm-pcie fd500000.pcie: No bus range found for /scb/pcie@7d500000, using [bus 00-ff]
[ 0.572391] brcm-pcie fd500000.pcie: MEM 0x0600000000..0x063fffffff -> 0x00c0000000
[ 0.572411] brcm-pcie fd500000.pcie: IB MEM 0x0000000000..0x007fffffff -> 0x0400000000
[ 0.573370] brcm-pcie fd500000.pcie: link up, 5.0 GT/s PCIe x1 (SSC)
[ 0.573452] brcm-pcie fd500000.pcie: PCI host bridge to bus 0000:00

- I have tried adding settings or options and changing the boot order with the eeprom image through usbboot, but it didn't work.
- I don't know if the message below, which can be seen when the official Raspberry Pi OS is installed, is a reliable message. 3.3V and 1.05V are being supplied normally.
(However, unlike the CM4 IO board, 3.3V and 1.05V are not separated into Digital and Analog. The same power line is applied.)
- I have applied the things I could refer to through VL805 (etc. SMI Pull-up, although it didn't seem to matter much in the CM4 IO Board circuit).

- supply vpcie3v3 not found, using dummy regulator
- supply vpcie3v3aux not found, using dummy regulator
- supply vpcie12v not found, using dummy regulator

I can upload additional materials needed for the advice if necessary.

Even if it's not a complete solution, I would like to know a good starting point that I couldn't find with AI or on the internet.

Thank you.

Statistics: Posted by rebel81 — Tue Sep 09, 2025 1:13 am

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