Bare metal, Assembly language • UART Peripheral not working with HC-06

Code:

.text.global startb startdelay:sub r7, r7, #1cmp r7, #0bne delaybx lrstatus_led_toggle:ldr r0, =sio_basemov r1, #1lsl r1, r1, #25str r1, [r0, #0x1c]bx lrstart:ldr r0, =reset_baseldr r7, =atomic_setadd r0, r0, r7// stuff to reset// bit 23 - UART1// bit 22 - UART0// bit 5 - SIO - IO_BANK0ldr r1, =0b10000000000000000100000str r1, [r0, #0]ldr r7, =0xf0000bl delay// Deassert the resetldr r0, =reset_basemov r1, #0str r1, [r0, #0]status_led_setup:// set GPIO25 to use sio - software controlldr r0, =io_bankmov r1, #5mov r7, #0xccstr r1, [r0, r7]// enable outputldr r0, =sio_basemov r1, #1lsl r1, r1, #25str r1, [r0, #0x24]// set output lowstr r1, [r0, #0x18]uart:// set GPIO0 and GPIO1 to use uart0ldr r0, =io_bankmov r1, #2str r1, [r0, #0x4]str r1, [r0, #0xc]// Action list 4.2.7. Programmer's Model// enable Peripheral clock 2.15.3ldr r0, =clocks_basemov r1, #1lsl r1, r1, #11str r1, [r0, #0x48]ldr r0, =uart0_base// Set the baud rate divisors 4.2.3.2ldr r1, =813str r1, [r0, #0x24]mov r1, #51str r1, [r0, #0x28]// enable FIFOs bit 4// Set format bit 6:5// b11 = 8 bits; b10 = 7; bits b01 = 6 bits; b00 = 5 bits// Table 432. UARTLCR_H Registermov r1, #0b1110000str r1, [r0, #0x2c]// Enable FIFOs 4.2.8 Table 433 UARTCR Registerldr r1, =0b11000000001str r1, [r0, #0x30]// enable DREQ signals as in uart_init()mov r1, #0b11str r1, [r0, #0x48]bl status_led_toggle// delayldr r7, =0xf000bl delaysend:ldr r0, =uart0_basemov r1, #65str r1, [r0, #0]ldr r7, =0xf0000bl delaybl status_led_toggleb sendend:b end.equ atomic_reset_base, 0x4000e000.equ reset_base, 0x4000c000.equ io_bank, 0x40014000.equ sio_base, 0xd0000000.equ pio0_base, 0x50200000.equ pio1_base, 0x50300000.equ clocks_base, 0x40008000.equ uart0_base, 0x40034000.equ atomic_xor, 0x1000.equ atomic_set, 0x2000.equ atomic_clear, 0x3000