More details here: https://developer.arm.com/documentation ... 6724325622
So far what I've seen is that if you use only the first 64 vectors (first 48 interrupts), it's enough to align to 256.
Also:
(I guess this happened in this case)
So far what I've seen is that if you use only the first 64 vectors (first 48 interrupts), it's enough to align to 256.
Also:
But if want to keep your (in)sanity, then follow basically what @czietz noted, align to 512 or risk warp around.On RP2350, only the lower 46 IRQ signals are connected to system-level interrupt sources, and IRQs 46 to 51 are
hardwired to zero (never firing). These six spare interrupts, referred to as SPAREIRQ_IRQ_0 through SPAREIRQ_IRQ_5 in the
table, are deliberately reserved for the cores to interrupt themselves (via the Arm NVIC_ISPR0 registers or the Hazard3
MEIFA CSR), for example, when an interrupt handler wants to schedule a "bottom half" handler for work that must be
done after exiting the interrupt handler, but before returning to the code running in the foreground.
(I guess this happened in this case)
The silicon vendor must configure the required alignment of the vector tables, which depends on the number of interrupts implemented. The minimum alignment is 32 words, enough for up to 16 interrupts. For more interrupts, adjust the alignment by rounding up to the next power of two. For example, if you require 21 interrupts, the alignment must be on a 64-word boundary because the required table size is 37 words, and the next power of two is 64.
Statistics: Posted by gmx — Fri May 02, 2025 11:42 pm