Is it possible to set the clock freq myself? Or do I have to mess with the drivers and recompile them?All our drivers correctly advertise a V4L2_CID_LINK_FREQUENCY property, and should have the correct values in the relevant device tree files. (The exception may be ov5647 as it is so old)
https://github.com/raspberrypi/linux/tr ... /media/i2c
https://github.com/raspberrypi/linux/tr ... s/overlays
MIPI D-PHY is Double Data Rate (DDR), so transfers a bit on both clock edges. The data rate per lane is therefore twice the link frequency.
Statistics: Posted by hasanthesyrian — Sat Apr 12, 2025 4:52 pm