Apologies I should have mentioned I tried increasing the clock using the default stage 2 boot, but nothing. I went up to 128 with it only working with a generic stage 2 boot at CLKDIV 8.
It could maybe be related to the CS issue - hence my debug suggestion of going even slower on the clock to see if that makes it go away.
Certainly your new flash layout looks good.
Honestly, I'm not sure, I had the space...why not. It's not like the signals will be fast, I thought I would prioritize reducing dc resistance. At these low speeds, I doubt it would make a difference whether they are large or small. I just get worried the traces will be too small and I air on the side of making them larger....as overkill as it might be.I do wonder why you are using super-wide tracks for digital signals on the inner layer (they look a width more appropriate for power connections). No reason to think it will stop it working, just seems a bit odd.
Statistics: Posted by lpearl — Thu Feb 06, 2025 4:59 am