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Interfacing (DSI, CSI, I2C, etc.) • Re: GPIO pin (GND to be specific) current sink limit

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@pcmanbob

1. Current at node source node of MOSFET = whatever current draw from the load (FAN)
2. The node immediately below pin 3 also sees the same current in [1] above
3. My confusion is this: How does the current from the [2] split so that current -- in yellow line -- that's going into the GND pin of GPIO doesn't violate the current sink specifications? In order to make sure the current in yellow line doesn't violate spec, shouldn't I have some resistance in series to the GND pin 30

Statistics: Posted by microberry — Fri Aug 23, 2024 10:38 pm



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