Note that this is not the default RP2040 behaviour. If your scope shot is really showing the QSPI clock running at 125MHz, then you have a very non-standard configuration.Given the the brains over at RPi decided to run some transactions near this flash's limits (125MHz transaction, 133MHz maximum clock according to flash datasheet),
The QSPI clock is generated via a divider from the RP2040 clk_sys. The minimum divider is 2, and the default clk_sys in the SDK is 125MHz, so the normal QSPI speed is 62.5MHz in a standard SDK application. The initial boot from the bootrom is slower, and if you are building your application with the SDK then you can adjust the divider to run the QSPI slower if your system requires it - this is the PICO_FLASH_SPI_CLKDIV setting in your board file mentioned earlier.
So the only way you can get 125MHz on the QSPI clk is if you are heavily overclocking the RP2040 (to 250MHz) and then using the standard /2 divider.
Using such a severe overclock is of course asking for trouble (I would never do so in professional applications), but it still might work if you set PICO_FLASH_SPI_CLKDIV to 4.
Statistics: Posted by arg001 — Tue Jul 30, 2024 5:58 pm