Compute Module • Re: Issues interfacing VL805 with CM4

Code:

[    1.130360] PCI: CLS 0 bytes, default 64[    1.153876] brcm-pcie fd500000.pcie: host bridge /scb/pcie@7d500000 ranges:[    1.153915] brcm-pcie fd500000.pcie:   No bus range found for /scb/pcie@7d500000, using [bus 00-ff][    1.153958] brcm-pcie fd500000.pcie:      MEM 0x0600000000..0x063fffffff -> 0x00c0000000[    1.153995] brcm-pcie fd500000.pcie:   IB MEM 0x0000000000..0x01ffffffff -> 0x0400000000[    1.155272] brcm-pcie fd500000.pcie: PCI host bridge to bus 0000:00[    1.155301] pci_bus 0000:00: root bus resource [bus 00-ff][    1.155316] pci_bus 0000:00: root bus resource [mem 0x600000000-0x63fffffff] (bus address [0xc0000000-0xffffffff])[    1.155366] pci 0000:00:00.0: [14e4:2711] type 01 class 0x060400[    1.155565] pci 0000:00:00.0: PME# supported from D0 D3hot[    1.159111] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring[    1.159321] pci_bus 0000:01: supply vpcie3v3 not found, using dummy regulator[    1.159528] pci_bus 0000:01: supply vpcie3v3aux not found, using dummy regulator[    1.159590] pci_bus 0000:01: supply vpcie12v not found, using dummy regulator[    1.587474] brcm-pcie fd500000.pcie: link down[    1.587757] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01[    1.587793] pci 0000:00:00.0: PCI bridge to [bus 01][    1.588320] pcieport 0000:00:00.0: PME: Signaling with IRQ 27[    1.588701] pcieport 0000:00:00.0: AER: enabled with IRQ 27[    1.589212] pci_bus 0000:01: busn_res: [bus 01] is released[    1.589735] pci_bus 0000:00: busn_res: [bus 00-ff] is released